In the design of integrated-circuit devices, decreasing the resistance-capacitance (RC) delay time in interconnect elements between the circuit elements, such as transistors, is an important goal for increasing the speed of signal transmission between circuit elements. In order to reduce the RC delay time, a known strategy is to use a porous ultra-low-k (P-ULk) insulator material to decrease the capacitance, and to use Copper-containing material for the interconnect elements for providing a low resistance.
The use of Copper in interconnect elements, however, requires the provision of a diffusion barrier between an interconnect element and the neighboring dielectric layer. For keeping the resistance value of the interconnect element low even in the presence of the diffusion barrier, a thin conformal metallic diffusion-barrier layer stack, for instance containing a layer of TaN and a layer of Ta is used. This allows the low-resistive Copper occupying a large volume in an opening of the dielectric layer provided for the interconnect element or a via vertically connecting interconnect elements on different metal levels of an interconnect stack.
However, this strategy has several disadvantages. The precursor used for the metallic diffusion-barrier deposition may deeply penetrate into the dielectric material, causing device performance issues and a decrease of reliability. Furthermore, the adhesion between the known P-ULk/metal barrier/Copper-containing material layer sequences is poor. Among other problem, this leads to a poor electromigration performance. Electromigration causes premature device failure.
The use of TaN/Ta barrier-layer stack between a Copper-containing feature and the dielectric layer has the further disadvantage that a Ta oxidation or Copper corrosion at the Cu/Ta interface occurs in the context of the deposition of a CoWP layer on top of the feature, which damages the diffusion-barrier layer stack and leads to out-diffusion of Copper into the dielectric layer.